library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity contNb_Lento_2 is
	generic(
		N: natural := 4;
		CICLOS: natural := 10
	);
	port(
		clk_i	: in std_logic;
		rst_i	: in std_logic;
		ena_i	: in std_logic;
		q_o		: out std_logic_vector(N-1 downto 0);
		ena_o	: out std_logic
	);
end;

architecture contNb_Lento_2_arq of contNb_Lento_2 is
	-- Parte delcarativa
	
begin
	-- Parte descriptiva

	process(clk_i)
		variable cicleCount: integer := 0;
		variable count: unsigned(N-1 downto 0);
	begin
		if rising_edge(clk_i) then
			if rst_i = '1' then
				count := (N-1 downto 0 => '0');
				ena_o <= '0';
			elsif ena_i = '1' then
				cicleCount := cicleCount + 1;
				if cicleCount = CICLOS then
					cicleCount := 0;
					count := count + 1;
					ena_o <= '1';
				else
					ena_o <= '0';
				end if;
			end if;
		end if;
		q_o <= std_logic_vector(count);
	end process;
end;