Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT Target Device: xc3s500e
Project ID (random number) 456cc196ddb34ca0bb84ddd35649398c.6D6860E508FC4FCFA6146E2EB098945F.12 Target Package: fg320
Registration ID __0_0_0 Target Speed: -4
Date Generated 2016-08-03T14:58:54 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz CPU Speed 2800 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Registers=84
  • Flip-Flops=84
 		MiscellaneousStatistics
  • AGG_BONDED_IO=10
  • AGG_IO=10
  • AGG_SLICE=96
  • NUM_4_INPUT_LUT=174
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=8
  • NUM_BUFGMUX=2
  • NUM_CYMUX=38
  • NUM_DCM=1
  • NUM_DP_RAM=16
  • NUM_LUT_RT=2
  • NUM_RAM32=52
  • NUM_RAMB16=1
  • NUM_SLICEL=62
  • NUM_SLICEM=34
  • NUM_SLICE_FF=77
  • NUM_XOR=37
 		NetStatistics
  • NumNets_Active=224
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=10
  • NumNodesOfType_Active_BRAMDUMMY=18
  • NumNodesOfType_Active_CLKPIN=76
  • NumNodesOfType_Active_CNTRLPIN=81
  • NumNodesOfType_Active_DOUBLE=540
  • NumNodesOfType_Active_DUMMY=601
  • NumNodesOfType_Active_DUMMYBANK=9
  • NumNodesOfType_Active_DUMMYESC=3
  • NumNodesOfType_Active_GLOBAL=29
  • NumNodesOfType_Active_HFULLHEX=7
  • NumNodesOfType_Active_HUNIHEX=11
  • NumNodesOfType_Active_INPUT=770
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=216
  • NumNodesOfType_Active_OUTPUT=194
  • NumNodesOfType_Active_PREBXBY=166
  • NumNodesOfType_Active_VFULLHEX=19
  • NumNodesOfType_Active_VLONG=4
  • NumNodesOfType_Active_VUNIHEX=33
  • NumNodesOfType_Vcc_BRAMDUMMY=1
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_INPUT=4
  • NumNodesOfType_Vcc_PREBXBY=3
  • NumNodesOfType_Vcc_VCCOUT=5
 SiteStatistics
  • IBUF-DIFFM=1
  • IOB-DIFFM=4
  • IOB-DIFFS=4
  • SLICEL-SLICEM=18
 		SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • DCM=1
  • DCM_DCM=1
  • IBUF=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=8
  • IOB_OUTBUF=8
  • IOB_PAD=8
  • RAMB16=1
  • RAMB16_RAMB16=1
  • RAMB16_RAMB16A=1
  • SLICEL=62
  • SLICEL_CYMUXF=22
  • SLICEL_CYMUXG=16
  • SLICEL_F=52
  • SLICEL_F5MUX=9
  • SLICEL_FFX=30
  • SLICEL_FFY=29
  • SLICEL_G=54
  • SLICEL_GNDF=14
  • SLICEL_GNDG=9
  • SLICEL_XORF=17
  • SLICEL_XORG=20
  • SLICEM=34
  • SLICEM_BYINVOUTUSED=8
  • SLICEM_BYOUTUSED=8
  • SLICEM_DIGUSED=8
  • SLICEM_F=34
  • SLICEM_F5MUX=26
  • SLICEM_F6MUX=8
  • SLICEM_FFX=10
  • SLICEM_FFY=8
  • SLICEM_G=34
  • SLICEM_WSGEN=34
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
 BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
 DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[6:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
 IBUF_INBUF
  • IBUF_DELAY_VALUE=[DLY0:1]
 IBUF_PAD
  • IOATTRBOX=[LVTTL:1] [LVCMOS33:1]
  • PULL=[PULLDOWN:1]
 IOB
  • O1=[O1_INV:0] [O1:8]
 IOB_OUTBUF
  • IN=[IN_INV:0] [IN:8]
 IOB_PAD
  • DRIVEATTRBOX=[8:8]
  • IOATTRBOX=[LVTTL:8]
  • SLEW=[SLOW:8]
 RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
 RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:1]
  • ENA=[ENA_INV:0] [ENA:1]
  • PORTA_ATTR=[1024X18:1]
  • SSRA=[SSRA_INV:0] [SSRA:1]
  • WEA=[WEA:1] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:1]
 SLICEL
  • BX=[BX_INV:0] [BX:20]
  • BY=[BY:6] [BY_INV:1]
  • CE=[CE:6] [CE_INV:5]
  • CIN=[CIN_INV:0] [CIN:16]
  • CLK=[CLK:39] [CLK_INV:0]
  • SR=[SR:31] [SR_INV:4]
 SLICEL_CYMUXF
  • 0=[0:22] [0_INV:0]
  • 1=[1_INV:0] [1:22]
 SLICEL_CYMUXG
  • 0=[0:16] [0_INV:0]
 SLICEL_F5MUX
  • S0=[S0:9] [S0_INV:0]
 SLICEL_FFX
  • CE=[CE:4] [CE_INV:5]
  • CK=[CK:30] [CK_INV:0]
  • D=[D:30] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:30]
  • FFX_SR_ATTR=[SRLOW:30]
  • LATCH_OR_FF=[FF:30]
  • SR=[SR:25] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:1] [SYNC:29]
 SLICEL_FFY
  • CE=[CE:6] [CE_INV:5]
  • CK=[CK:29] [CK_INV:0]
  • D=[D:28] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:27] [INIT1:2]
  • FFY_SR_ATTR=[SRLOW:27] [SRHIGH:2]
  • LATCH_OR_FF=[FF:29]
  • SR=[SR:21] [SR_INV:4]
  • SYNC_ATTR=[ASYNC:4] [SYNC:25]
 SLICEL_XORF
  • 1=[1_INV:0] [1:17]
 SLICEM
  • ALTDIG=[ALTDIG:8] [ALTDIG_INV:0]
  • BX=[BX_INV:0] [BX:26]
  • BY=[BY:34] [BY_INV:0]
  • CLK=[CLK:34] [CLK_INV:0]
  • SR=[SR:24] [SR_INV:10]
 SLICEM_BYINVOUTUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_BYOUTUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_DIGUSED
  • 0=[0:8] [0_INV:0]
 SLICEM_F
  • DI=[DI:34] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:8]
  • LUT_OR_MEM=[RAM:34]
 SLICEM_F5MUX
  • S0=[S0:26] [S0_INV:0]
 SLICEM_F6MUX
  • S0=[S0:8] [S0_INV:0]
 SLICEM_FFX
  • CK=[CK:10] [CK_INV:0]
  • D=[D:10] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:10]
  • FFX_SR_ATTR=[SRLOW:10]
  • LATCH_OR_FF=[FF:10]
  • SYNC_ATTR=[ASYNC:10]
 SLICEM_FFY
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:8]
  • FFY_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SYNC_ATTR=[ASYNC:8]
 SLICEM_G
  • DI=[DI:34] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:8]
  • LUT_OR_MEM=[RAM:34]
 SLICEM_WSGEN
  • CK=[CK:34] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:18]
  • WE=[WE_INV:10] [WE:24]
  • WE0=[WE0:26] [WE0_INV:0]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
 BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
 BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
 DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DCM_DCM
  • CLK0=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 IBUF
  • I=2
  • PAD=2
 IBUF_INBUF
  • IN=2
  • OUT=2
 IBUF_PAD
  • PAD=2
 IOB
  • O1=8
  • PAD=8
 IOB_OUTBUF
  • IN=8
  • OUT=8
 IOB_PAD
  • PAD=8
 RAMB16
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA=1
 RAMB16_RAMB16
  • ADDRA=1
  • DIA=1
  • DOA=1
 RAMB16_RAMB16A
  • ADDRA=1
  • ADDRA10=1
  • ADDRA11=1
  • ADDRA12=1
  • ADDRA13=1
  • ADDRA4=1
  • ADDRA5=1
  • ADDRA6=1
  • ADDRA7=1
  • ADDRA8=1
  • ADDRA9=1
  • CLKA=1
  • DIA=1
  • DOA=1
  • DOA0=1
  • DOA1=1
  • DOA10=1
  • DOA11=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA2=1
  • DOA3=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENA=1
  • SSRA=1
  • WEA=1
 SLICEL
  • BX=20
  • BY=7
  • CE=11
  • CIN=16
  • CLK=39
  • COUT=16
  • F1=52
  • F2=52
  • F3=39
  • F4=17
  • G1=52
  • G2=51
  • G3=50
  • G4=10
  • SR=35
  • X=20
  • XQ=30
  • Y=21
  • YQ=29
 SLICEL_CYMUXF
  • 0=22
  • 1=22
  • OUT=22
  • S0=22
 SLICEL_CYMUXG
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
 SLICEL_F
  • A1=50
  • A2=52
  • A3=39
  • A4=17
  • D=52
 SLICEL_F5MUX
  • F=9
  • G=9
  • OUT=9
  • S0=9
 SLICEL_FFX
  • CE=9
  • CK=30
  • D=30
  • Q=30
  • SR=29
 SLICEL_FFY
  • CE=11
  • CK=29
  • D=29
  • Q=29
  • SR=25
 SLICEL_G
  • A1=51
  • A2=51
  • A3=50
  • A4=10
  • D=54
 SLICEL_GNDF
  • 0=14
 SLICEL_GNDG
  • 0=9
 SLICEL_XORF
  • 0=17
  • 1=17
  • O=17
 SLICEL_XORG
  • 0=20
  • 1=20
  • O=20
 SLICEM
  • ALTDIG=8
  • BX=26
  • BY=34
  • BYINVOUT=8
  • BYOUT=8
  • CLK=34
  • DIG=8
  • F1=34
  • F2=34
  • F3=34
  • F4=34
  • F5=16
  • FXINA=8
  • FXINB=8
  • G1=34
  • G2=34
  • G3=34
  • G4=34
  • SLICEWE1=16
  • SR=34
  • X=8
  • XQ=10
  • Y=8
  • YQ=8
 SLICEM_BYINVOUTUSED
  • 0=8
  • OUT=8
 SLICEM_BYOUTUSED
  • 0=8
  • OUT=8
 SLICEM_DIGUSED
  • 0=8
  • OUT=8
 SLICEM_F
  • A1=34
  • A2=34
  • A3=34
  • A4=34
  • D=34
  • DI=34
  • WF1=34
  • WF2=34
  • WF3=34
  • WF4=34
  • WS=34
 SLICEM_F5MUX
  • F=26
  • G=26
  • OUT=26
  • S0=26
 SLICEM_F6MUX
  • 0=8
  • 1=8
  • OUT=8
  • S0=8
 SLICEM_FFX
  • CK=10
  • D=10
  • Q=10
 SLICEM_FFY
  • CK=8
  • D=8
  • Q=8
 SLICEM_G
  • A1=34
  • A2=34
  • A3=34
  • A4=34
  • D=34
  • DI=34
  • WG1=34
  • WG2=34
  • WG3=34
  • WG4=34
  • WS=34
 SLICEM_WSGEN
  • CK=34
  • WE=34
  • WE0=26
  • WE1=16
  • WSF=34
  • WSG=34
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 117 111 0 0 0 0 0
arwz 16 16 0 0 0 0 0
bitgen 140 140 0 0 0 0 0
bitinit 8 8 0 0 0 0 0
cse_server 15 15 0 0 0 0 0
elfcheck 145 144 0 0 0 0 0
libgen 20 20 0 0 0 0 0
map 176 150 0 0 0 0 0
netgen 19 19 0 0 0 0 0
ngcbuild 72 72 0 0 0 0 0
ngdbuild 188 187 0 0 0 0 0
obngc 5 5 0 0 0 0 0
par 150 145 0 0 0 0 0
platgen 26 19 0 0 0 0 0
psf2Edward 16 16 0 0 0 0 0
reportgen 19 19 0 0 0 0 0
trce 141 141 0 0 0 0 0
xdsgen 16 16 0 0 0 0 0
xps 15 15 0 0 0 0 0
xst 437 428 0 0 0 0 0
 
Help Statistics
Search words with results
phase shift ( 1 ) variable ( 1 )
Help files
/doc/usenglish/isehelp/pce_p_clock_period_relative.htm ( 3 ) /doc/usenglish/wizards/arwz/awz_db_dcmgen.htm ( 1 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/testbench_vhd
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Constraints Editor PROP_intProjectCreationTimestamp=2010-06-30T21:00:13
PROP_intWbtProjectID=6D6860E508FC4FCFA6146E2EB098945F PROP_intWbtProjectIteration=12
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.testbench_vhd PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s500e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=VHDL FILE_UCF=1
FILE_VHDL=5 FILE_XAW=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=24 NGDBUILD_NUM_FDE=2
NGDBUILD_NUM_FDR=30 NGDBUILD_NUM_FDRE=16 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=2 NGDBUILD_NUM_LUT2=6 NGDBUILD_NUM_LUT3=69 NGDBUILD_NUM_LUT4=33
NGDBUILD_NUM_MUXCY=39 NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_RAM16X1D=8
NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16_S18=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=37
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FD=24 NGDBUILD_NUM_FDE=2
NGDBUILD_NUM_FDR=30 NGDBUILD_NUM_FDRE=16 NGDBUILD_NUM_FDRSE=10 NGDBUILD_NUM_FDS=2
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=4
NGDBUILD_NUM_LUT1=2 NGDBUILD_NUM_LUT2=6 NGDBUILD_NUM_LUT3=69 NGDBUILD_NUM_LUT4=33
NGDBUILD_NUM_MUXCY=39 NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_PULLDOWN=1
NGDBUILD_NUM_RAM32X1S=10 NGDBUILD_NUM_RAM64X1S=8 NGDBUILD_NUM_RAMB16_S18=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=37
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=ieee, unisim, std
Fuse Resource Usage=2390 ms, 153520 KB
Total Signals=1845
Total Nets=1695
Total Blocks=428
Total Processes=503
Total Simulation Time=1 us
Simulation Resource Usage=0.59375 sec, 998666 KB
Simulation Mode=gui
Hardware CoSim=0