| encender_leds Project Status | |||
| Project File: | synth_lab.xise | Parser Errors: | No Errors |
| Module Name: | encender_leds | Implementation State: | Programming File Generated |
| Target Device: | xc3s500e-4fg320 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
120 Warnings (0 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Flip Flops | 77 | 9,312 | 1% | ||
| Number of 4 input LUTs | 172 | 9,312 | 1% | ||
| Number of occupied Slices | 96 | 4,656 | 2% | ||
| Number of Slices containing only related logic | 96 | 96 | 100% | ||
| Number of Slices containing unrelated logic | 0 | 96 | 0% | ||
| Total Number of 4 input LUTs | 174 | 9,312 | 1% | ||
| Number used as logic | 104 | ||||
| Number used as a route-thru | 2 | ||||
| Number used for Dual Port RAMs | 16 | ||||
| Number used for 32x1 RAMs | 52 | ||||
| Number of bonded IOBs | 10 | 232 | 4% | ||
| Number of RAMB16s | 1 | 20 | 5% | ||
| Number of BUFGMUXs | 2 | 24 | 8% | ||
| Number of DCMs | 1 | 4 | 25% | ||
| Average Fanout of Non-Clock Nets | 4.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Wed Aug 3 14:58:10 2016 | 0 | 119 Warnings (0 new) | 0 | |
| Translation Report | Current | Wed Aug 3 14:58:16 2016 | 0 | 1 Warning (0 new) | 0 | |
| Map Report | Current | Wed Aug 3 14:58:23 2016 | 0 | 0 | 3 Infos (0 new) | |
| Place and Route Report | Current | Wed Aug 3 14:58:42 2016 | 0 | 0 | 2 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Wed Aug 3 14:58:47 2016 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | Current | Wed Aug 3 14:58:54 2016 | 0 | 0 | 1 Info (0 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Current | Fri Aug 5 15:45:36 2016 | |
| WebTalk Report | Current | Wed Aug 3 14:58:54 2016 | |
| WebTalk Log File | Current | Wed Aug 3 14:59:06 2016 | |