Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2188600
date_generatedWed Aug 5 12:35:05 2020 os_platformWIN64
product_versionVivado v2018.1 (64-bit) project_id739b5dabddb34304996ef31885ee291e
project_iteration2 random_idd7e926b6-e6b1-45eb-9f6c-1c9c7d9287b1
registration_id210865404_0_0_206 route_designTRUE
target_devicexc7a35ti target_familyartix7
target_packagecsg324 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-7360U CPU @ 2.30GHz cpu_speed2304 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram2.000 GB total_processors1

vivado_usage
gui_handlers
addsrcwizard_specify_hdl_netlist_block_design=1 addsrcwizard_specify_or_create_constraint_files=1 basedialog_ok=6 boardchooser_board_table=2
constraintschooserpanel_add_files=1 filesetpanel_file_set_panel_tree=23 flownavigatortreepanel_flow_navigator_tree=4 gettingstartedview_create_new_project=1
gettingstartedview_open_project=1 hcodeeditor_search_text_combo_box=5 msgtreepanel_message_view_tree=1 pacommandnames_add_sources=4
pacommandnames_auto_update_hier=4 projectnamechooser_project_name=1 rdicommands_delete=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3
srcmenu_ip_hierarchy=4 syntheticastatemonitor_cancel=1
java_command_handlers
addsources=4 editdelete=1 newproject=1 openproject=1
runbitgen=4 showview=1
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bscane2=1 bufg=2 carry4=10 fdre=126
fdse=2 gnd=14 ibuf=6 lut2=3
lut3=2 lut4=5 lut5=52 lut6=97
obuf=8 ramb18e1=1 ramd32=24 ramd64e=8
rams32=8 vcc=5
pre_unisim_transformation
bscane2=1 bufg=2 carry4=10 fdre=126
fdse=2 gnd=14 ibuf=6 lut2=3
lut3=2 lut4=5 lut5=2 lut6=47
lut6_2=50 obuf=8 ram32m=4 ram64m=2
ramb18e1=1 vcc=5

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=126 srls_augmented=0
srls_newly_gated=0 srls_total=0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-17=168

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.040844 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.066231
die=xc7a35ticsg324-1L dsp_output_toggle=12.500000 dynamic=2.643844 effective_thetaja=4.8
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.066272 input_toggle=12.500000 junction_temp=38.0 (C)
logic=1.152690 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=2.710075
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=csg324
pct_clock_constrained=2.000000 pct_inputs_defined=0 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=1.384039 simulation_file=None speedgrade=-1L
static_prob=False temp_grade=industrial thetajb=6.8 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.8 user_junc_temp=38.0 (C)
user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.018000
vccadc_total_current=0.018000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.001732 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.011810
vccaux_total_current=0.013542 vccaux_voltage=1.800000 vccbram_dynamic_current=0.003020 vccbram_static_current=0.000167
vccbram_total_current=0.003186 vccbram_voltage=0.950000 vccint_dynamic_current=2.730215 vccint_static_current=0.009594
vccint_total_current=2.739809 vccint_voltage=0.950000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.013380 vcco33_static_current=0.001000
vcco33_total_current=0.014380 vcco33_voltage=3.300000 version=2018.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=1.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=1.00
ramb18e1_only_used=1 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bscane2_functional_category=Others bscane2_used=1 bufg_functional_category=Clock bufg_used=2
carry4_functional_category=CarryLogic carry4_used=10 fdre_functional_category=Flop & Latch fdre_used=124
fdse_functional_category=Flop & Latch fdse_used=2 ibuf_functional_category=IO ibuf_used=6
lut2_functional_category=LUT lut2_used=3 lut3_functional_category=LUT lut3_used=4
lut4_functional_category=LUT lut4_used=6 lut5_functional_category=LUT lut5_used=54
lut6_functional_category=LUT lut6_used=80 obuf_functional_category=IO obuf_used=8
ramb18e1_functional_category=Block Memory ramb18e1_used=1 ramd32_functional_category=Distributed Memory ramd32_used=24
ramd64e_functional_category=Distributed Memory ramd64e_used=8 rams32_functional_category=Distributed Memory rams32_used=8
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=105 lut_as_logic_util_percentage=0.50 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=24 lut_as_memory_util_percentage=0.25 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=126 register_as_flip_flop_util_percentage=0.30
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=129 slice_luts_util_percentage=0.62
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=126 slice_registers_util_percentage=0.30
fully_used_lut_ff_pairs_fixed=0.30 fully_used_lut_ff_pairs_used=3 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=105 lut_as_logic_util_percentage=0.50
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=24 lut_as_memory_util_percentage=0.25
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=64
lut_ff_pairs_with_one_unused_lut_output_fixed=64 lut_ff_pairs_with_one_unused_lut_output_used=46 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=75 lut_flip_flop_pairs_util_percentage=0.36 slice_available=8150 slice_fixed=0
slice_used=47 slice_util_percentage=0.58 slicel_fixed=0 slicel_used=34
slicem_fixed=0 slicem_used=13 unique_control_sets_used=14 using_o5_and_o6_fixed=14
using_o5_and_o6_used=16 using_o5_output_only_fixed=16 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=8
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=648586 bogomips=0 bram18=1 bram36=0
bufg=0 bufr=0 ctrls=14 dsp=0
effort=2 estimated_expansions=316812 ff=126 global_clocks=2
high_fanout_nets=0 iob=14 lut=129 movable_instances=362
nets=432 pins=2481 pll=0 router_runtime=0.000000
router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35ticsg324-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=Sistema_Base -verilog_define=default::[not_specified]
usage
elapsed=00:00:59s hls_ip=0 memory_gain=499.910MB memory_peak=745.758MB